Thilak's 12+ years (2011 to 2023) journey at Intel
Skillset
Hardware Languages: Verilog, System Verilog
Scripting: Perl, Tcl, Linux.
Third party EDA Tools: VCS, Verdi, Conformal, ESP, NCSIM, OVM, Spyglass (Lint, CDC, DFT and LP), Design Compiler, Adobe Frame Maker, Nanotime, XA.
Utility Software: Adobe Premiere Pro and Lightroom.
Scripting: Perl, Tcl, Linux.
Third party EDA Tools: VCS, Verdi, Conformal, ESP, NCSIM, OVM, Spyglass (Lint, CDC, DFT and LP), Design Compiler, Adobe Frame Maker, Nanotime, XA.
Utility Software: Adobe Premiere Pro and Lightroom.
Work Experience
[Nov 2021 - Dec 2023] - Programmable Solutions Group: Senior SoC Design Engineer
Responsible for:
Logic design and integration of a complex SoC including high-performance CPU-based SoC designs CPU, security device management, high-performance I/O interfaces, and high-speed transceivers, network-on-chip, with configurable logic and memory array.
Contribute to the development of next-generation structured ASIC products that will be used in 5G, AI, IoT, and embedded applications.
[Jun 2021 - Nov 2021] - Xeon Engineering Group: SoC Design Engineer
Responsible for:
Integration of complex IP's into SoC.
Developing glue logic at SoC level.
Running, analyzing and fixing various quality check tools and flows such as CDC/RDC, lint, VCLP, Fishtail etc.
Design and integration methodology development and enforcement
Working with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.
[Aug 2016 - May 2021] - Data Center Group: Design automation engineer, supporting Front end tool and flows
Primary/Secondary support for Intel's proprietary environment for Front end design.
Enabled and developed flows for several front end tools, focused on design and verification.
Helped define Mixed signal verification methodologies using VCS-XA.
Identified, defined & published best practices for the various aspects related to RTL development, quality checks and back-end handoff
Architected and developed Perl based Packaging/encryption flow to support an external customer. This flow consolidated entire design from Intel’s proprietary environment into a single directory, followed by encryption, compilation and tests execution using VCD replay feature in VCS.
[Jan 2014 - Aug 2016] - Intel Custom Foundry: Design automation engineer,
Owned enabling and support for Front end tool and flows.
Architected and developed FEV flows for ASIC and Custom designs using Cadence Conformal tool.
Enhanced, optimized and enabled flows using Conformal and Spyglass to support low power designs. This effort enabled verification flows to be in line with rest of Intel SoC products.
Designed and setup regression suite for FEV and ESP using Perl. This effort enabled quality checks on the tool binary at the first point of entry, thus filtering previous issues and/or crashes.
Architected and delivered Perl based MBIST validation automation, which helped the team to become a best-in-class service provider, which resulted in increase of completeness as an organization.
Developed custom automation scripts for various customers within the organization. These automation scripts were designed to automate code compilation, run regression periodically and log results in html, to be reviewed by management to assess the health and to determine risk factors.
Led task force and drove several ESP tool issues to closure, by working with stakeholders, tracking progress, providing work around, thus enabling memory team to verify IPs on schedule.
[Aug 2011 - Jan 2014] - Platform Verification Engineering: RTL development and verification engineer
RTL development for Intel proprietary IP for Built in Self Test.
Integration and IP into SoCs.
Program management for Center of Excellence (CoE) process development and establishment.
Architecture and RTL development of command control blocks in Intel DFx IP to generate stress patterns for DDR/LPDDR using JEDEC algorithms.
Validation lead of Intel IP to test PCIe, USB3 and SATA interfaces across multiple products.
Responsible for:
Logic design and integration of a complex SoC including high-performance CPU-based SoC designs CPU, security device management, high-performance I/O interfaces, and high-speed transceivers, network-on-chip, with configurable logic and memory array.
Contribute to the development of next-generation structured ASIC products that will be used in 5G, AI, IoT, and embedded applications.
[Jun 2021 - Nov 2021] - Xeon Engineering Group: SoC Design Engineer
Responsible for:
Integration of complex IP's into SoC.
Developing glue logic at SoC level.
Running, analyzing and fixing various quality check tools and flows such as CDC/RDC, lint, VCLP, Fishtail etc.
Design and integration methodology development and enforcement
Working with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.
[Aug 2016 - May 2021] - Data Center Group: Design automation engineer, supporting Front end tool and flows
Primary/Secondary support for Intel's proprietary environment for Front end design.
Enabled and developed flows for several front end tools, focused on design and verification.
Helped define Mixed signal verification methodologies using VCS-XA.
Identified, defined & published best practices for the various aspects related to RTL development, quality checks and back-end handoff
Architected and developed Perl based Packaging/encryption flow to support an external customer. This flow consolidated entire design from Intel’s proprietary environment into a single directory, followed by encryption, compilation and tests execution using VCD replay feature in VCS.
[Jan 2014 - Aug 2016] - Intel Custom Foundry: Design automation engineer,
Owned enabling and support for Front end tool and flows.
Architected and developed FEV flows for ASIC and Custom designs using Cadence Conformal tool.
Enhanced, optimized and enabled flows using Conformal and Spyglass to support low power designs. This effort enabled verification flows to be in line with rest of Intel SoC products.
Designed and setup regression suite for FEV and ESP using Perl. This effort enabled quality checks on the tool binary at the first point of entry, thus filtering previous issues and/or crashes.
Architected and delivered Perl based MBIST validation automation, which helped the team to become a best-in-class service provider, which resulted in increase of completeness as an organization.
Developed custom automation scripts for various customers within the organization. These automation scripts were designed to automate code compilation, run regression periodically and log results in html, to be reviewed by management to assess the health and to determine risk factors.
Led task force and drove several ESP tool issues to closure, by working with stakeholders, tracking progress, providing work around, thus enabling memory team to verify IPs on schedule.
[Aug 2011 - Jan 2014] - Platform Verification Engineering: RTL development and verification engineer
RTL development for Intel proprietary IP for Built in Self Test.
Integration and IP into SoCs.
Program management for Center of Excellence (CoE) process development and establishment.
Architecture and RTL development of command control blocks in Intel DFx IP to generate stress patterns for DDR/LPDDR using JEDEC algorithms.
Validation lead of Intel IP to test PCIe, USB3 and SATA interfaces across multiple products.
Conference Publications
“Interactive Response System,” Thilak Kumar P R, Rashmi L S, Vinay Yadav R, Abdul Kabeer, Surya Prasad J, International Conference on Management Technology for Educational Practices, Bangalore, India, July 2009.
“A Flexible Database Security System Using ibutton Access Control Policies,” Surya Prasad J, Thilak Kumar P R, Rashmi L S, Vinay Yadav R, Mithun Kumar and Revanasiddappa M, National Conference on Engineering, Technology and Architecture, Bangalore, India, April, 2009.
“On the Design of Low-Power CMOS Comparators with Programmable Hysteresis,” Paul M. Furth, Member, IEEE, Yen-Chun Tsen, Vishnu B. Kulkarni and Thilak K. Poriyani House Raju, IEEE international Midwest Symposium on Circuit and Systems, Seattle, Washington, August 2010.
“A Flexible Database Security System Using ibutton Access Control Policies,” Surya Prasad J, Thilak Kumar P R, Rashmi L S, Vinay Yadav R, Mithun Kumar and Revanasiddappa M, National Conference on Engineering, Technology and Architecture, Bangalore, India, April, 2009.
“On the Design of Low-Power CMOS Comparators with Programmable Hysteresis,” Paul M. Furth, Member, IEEE, Yen-Chun Tsen, Vishnu B. Kulkarni and Thilak K. Poriyani House Raju, IEEE international Midwest Symposium on Circuit and Systems, Seattle, Washington, August 2010.
Education
[2009 - 2011]: M.S in Electrical Engineering at New Mexico State University (NMSU), USA.
Specialization: VLSI GPA: 3.84/4.00
Thesis: Low-Power, high input swing, AC coupled biometric amplifier.
[2005 - 2009]: B.E in Electronics & Communication Engineering, PESIT (South), Bangalore, INDIA.
[2003 - 2005]: Pre-university course from Christ Junior College, Bangalore, India. Specialization: Physics, Chemistry, Mathematics and Biology.
[1991 - 2003]: Baldwin Boys High School, Hosur Road, Bangalore, India.
Graduation Award: Prestigious Baldwin blue badge for all-round performance.
Specialization: VLSI GPA: 3.84/4.00
Thesis: Low-Power, high input swing, AC coupled biometric amplifier.
[2005 - 2009]: B.E in Electronics & Communication Engineering, PESIT (South), Bangalore, INDIA.
[2003 - 2005]: Pre-university course from Christ Junior College, Bangalore, India. Specialization: Physics, Chemistry, Mathematics and Biology.
[1991 - 2003]: Baldwin Boys High School, Hosur Road, Bangalore, India.
Graduation Award: Prestigious Baldwin blue badge for all-round performance.